Abstract—Many applications for digital processing are steadily increasing in radio frequency signal processing from analog to digital. ADPLL plays a vital role in digital signal processing. Several ADPLL models were introduced in the past. However, in those models, the power dissipation gets increased due to the delay in the lock state. Due to the generated digital noise, the system leads the output signal with inherent phase noise and does not undergo the frequency division process. Therefore, a novel Hilbert-Huang based All Digital Phase Locked Loop (HH-ADPLL) was proposed to make the ADPLL into the locked state. The input reference signal is initially entered in the Hilbert-Huang transform to extract the analytic component and generate the up and down signals. By eliminating the higher frequency part from these signals, the up/down counter produces borrow and carry signals. The carry and borrow signals are fed into the increment decrement counter to produce the output signal. At last, input and output signal matching is carried out in the phase detector module, and ADPLL enters a locked state. The presented HH-ADPLL is implemented in Artix-7 FPGA, and the efficiency is validated in terms of stability, phase error, power dissipation, combinational delay, and performance improvement computed.